1. Field of the Invention
The present invention relates to voltage hold circuits which holds an input signal voltage, and clock synchronization circuits including the voltage hold circuits.
2. Description of the Related Art
A related art having been provided in clock synchronization circuits for keeping the phase difference between an externally inputted reference clock signal and an output signal constant holds the voltage value of a control signal extracted from an inputted reference clock signal to be inputted to an oscillator configured to control the frequency of an output signal. When a reliable reference clock signal cannot be obtained due to some trouble, a signal of the held voltage is inputted to the oscillator. In this related art, an A/D converter is used.
As a voltage hold circuit, an analog sample-hold circuit is also known. In the sample-hold circuit, a voltage is held by storing a charge in a capacitor.
The A/D converter is, however, relatively costly. In particular, the related art using the A/D converter and a D/A converter needs to use an expensive A/D converter and D/A converter of good characteristics, especially linearity, to increase accuracy.
Also, in the sample-hold circuit, the charge stored in the capacitor is released with time, and thus the sample-hold circuit cannot hold the voltage for a long time.